Embedded Systems / Edge AI / Design Verification
Stavan Rupareliya
Embedded Software Engineer with 6+ years of experience in Edge AI, Embedded Linux, and SoC platforms. Transitioning into Design Verification with a strong foundation in Digital Design and Verilog HDL.
DV_ENGINEER_CORE
6+ years
Verilog, C/C++, Python, Linux, debugging, validation, and hardware-software integration.
verification_trace.vcd
PASS
Experience
Verification mindset with strong embedded systems depth
Dec 2025 - Present
Mantra Smart Identity (Mantra Softech) Sr. AI Research Engineer L1
Ahmedabad, India
- Designed, developed, and optimized computer vision models and GStreamer-based media pipelines for an Edge AI product, owning the end-to-end model lifecycle (development, training, conversion/optimization, and deployment) to enable real-time video analytics on embedded platforms.
- Conducted market research to analyze competitor products and industry trends, providing insights that guided product strategy and feature development.
Mar 2025 - Oct 2025
Tata Elxsi Limited Senior Software Engineer
Bangalore, India • Client: Comcast Corporation
- Developed AI/ML-based text and image summarization pipelines for multimedia applications on embedded platforms for Comcast, leveraging deep learning models for efficient content understanding and compression.
- Deployed and optimized AI inference pipelines on edge devices within embedded Linux environments, with a focus on performance profiling, debugging, and resource optimization.
Jul 2021 - Mar 2025
eInfochips (An Arrow Company) Software Engineer
Ahmedabad, India
- Designed and implemented a video analytics solution using C/C++ and Python, integrating deep learning and computer vision models with embedded hardware for real-time edge inference. Led hardware-software co-design efforts, bridging embedded systems with AI pipelines for seamless integration and deployment.
- Applied quantization and pruning techniques to computer vision models, achieving high accuracy with reduced computational overhead. Built a camera simulator with a modular image processing pipeline, facilitating rapid prototyping and client POC validation.
- Collaborated directly with U.S. and European clients, collaborating across engineering, product, and client teams to deliver solutions within agile development cycles.
Jan 2021 - Jun 2021
eInfochips (An Arrow Company) Project Trainee Engineer
Ahmedabad, India
- Completed training in C++, Python, embedded systems, and Linux internals with hands-on system programming and memory management projects.
- Contributed to client deliverables and assisted in building future project PoCs.
Projects
Selected verification and hardware-facing work
FIFO Design and Verification | RTL Design
Verilog · EDA PlaygroundDesigned a parameterized synchronous FIFO in Verilog RTL with configurable depth and data width, implementing read/write pointer logic and full/empty flag generation for reliable data buffering between clock-synchronous interfaces. The design was validated on EDA Playground with a self-checking testbench covering overflow, underflow, reset behavior, and simultaneous read and write pointer logic to ensure functional correctness.
5K random cycles
5 configurations
PASS open-source CI
UART Transmitter & Receiver | RTL Design
Verilog · EDA PlaygroundDesigned a UART transmitter and receiver in Verilog RTL with configurable baud rate, implementing FSM-based control for start/stop bit framing, serial-to-parallel data conversion, and parity generation/checking for reliable serial communication. The design was validated on EDA Playground using directed testcases and loopback testing, verifying data integrity across multiple baud rates and error conditions such as framing and parity errors.
3 baud rates
3 parity modes
PASS error injection
Binary Artificial Neural Network | ASIC Design
Verilog · ModelSim · SynopsysDesigned an RTL logic single-layer Binary Convolutional Neural Network which constituted a max-pooling layer on a randomized input matrix and kernel matrix extracted from 2 SRAMs using Verilog. The design was validated using ModelSim, with Synopsys Design Compiler synthesis targeting minimum area and maximum throughput.
2 SRAM matrices
300 random tests
3 geometries
Publications & talks
Research, teaching, and presentations
Technical Publications
-
"Real-time detection and identification of plant leaf diseases using convolutional neural networks on an embedded platform"
The Visual Computer, Springer, 2020.
Paper Link ↗ -
"Real-time Face Mask Detection System on Edge using Deep Learning and Hardware Accelerators"
2nd International Conference on Communication, Computing and Industry 4.0 (C2I4), IEEE, 2021.
Paper Link ↗ -
"Real-Time Tomato Detection, Classification, and Counting System Using Deep Learning and Embedded Systems"
International e-Conference on Intelligent Systems and Signal Processing, Springer, 2021.
Paper Link ↗ -
"Face Mask Detection and Counting Using Deep Learning and Embedded Systems"
Advances in VLSI, Communication, and Signal Processing, Springer, 2022.
Paper Link ↗
Invited Talks & Guest Lectures
-
Nirma University, Institute of Technology Jul 2026
Delivered an invited expert talk on "Edge AI and Vision" under the STTP program, presenting "Deep Dive into Edge AI: Concepts to Deployment". -
Indore Institute of Science and Technology (IIST), Indore Jun 2026
Invited talk on "Edge AI" at Adratim Adhiratham 2.0, covering AI hardware accelerators, computer vision, optimization pipelines, and deployment. -
Nirma University STTP Sep 2024
Represented eInfochips (An Arrow Company) as an Expert Lecturer for the Faculty Development Program (FDP), delivering a session on "Edge Computing and Computer Vision". -
Nirma University, M.Tech Students Aug 2024
Delivered an Industry Expert Lecture on "Edge Computing and Computer Vision" for M.Tech students specializing in VLSI and Embedded Systems. -
Nirma University, B.Tech Students Jan 2024
Delivered an Industry Expert Lecture on "Embedded AI & Computer Vision Applications", covering real-time AI deployment and embedded optimization.
Skill map
Technical expertise and competencies
Technology
Concepts
Languages
Protocols & Tools
Operating Systems
Education & Credentials
Academic foundation and professional certifications
Education
-
Jun 2018 - Jun 2020
Master of Technology (M.Tech)
Embedded Systems Engineering
Institute of Technology, Nirma University, Ahmedabad, India
-
Jun 2012 - Jun 2016
Bachelor of Engineering (B.E)
Instrumentation and Control Engineering
Atmiya Institute of Technology, Gujarat Technological University (GTU), Rajkot, India
Certifications & Awards
Maven Silicon Certifications
-
Digital Design – Hands-on
Combinational & sequential circuits, FSMs, and memories. -
Verilog HDL – Hands-on
Practical RTL design, sequential logic, FSMs, and simulation. -
VLSI System On Chip (SoC) Design – Overview
SoC design flow, architecture, IP integration, RTL design, and verification. -
Verification Methodology Overview
SystemVerilog, UVM concepts, testbench architecture, and coverage.
Industry Recognition
-
Core Value Award - Customer First 2024
For prioritizing customer needs and ensuring outstanding positive experience. -
Pat On The Back Award 2022
For exemplary performance and significant contributions to an image processing project.
Contact